Capability of pause refresh of a memory device is widely changed responsive to ambient temperature. Temperature compensation of a self-refresh period is the technique of controlling the refresh period for coping with the temperature dependency of the capability of pause refresh. If the technique of temperature compensation of the self-refresh period is brought to completion, it is possible to reduce the data retention current by one order of magnitude at ambient temperature as compared with that at elevated temperatures (upper limit of the guaranteed temperature). It is however technically difficult to design a circuit showing extensive temperature traceability suited to a device, such that there lacks an efficacious circuit designing technique.
The temperature compensation technique, so far proposed, may roughly be classified into the following two types:
(a) the technique in which temperature-dependent device parameters, such as the current of the MOS transistor, are detected by some means and converted into the refresh period, for example, the thermometer technique of monitoring the temperature to control the refresh period, or the technique of monitoring the cell leakage characteristics to control the refresh period, termed the ‘cell leakage monitor system’ in the present specification; and
(b) the technique of directly reading and writing plural memory cells that are for data retention, and determining the refresh period from the status of occurrence status of error.
Recently, a mobile SDRAM (Synchronous DRAM), characterized by the low data retention current, has been presented to the market. The products of this type basically uses the above technique (a).
Typical of the above technique (a) is the thermometer (temperature sensor) circuit. The refresh period controlling method, employing the thermometer circuit (thermometer system), detects e.g. minute temperature change of the level of the reference voltage (Vref) in a temperature sensor device (temperature sensor) and, based on the prevailing temperature information, elongates the refresh period by carrying out frequency-division, such as by doubling, quadrupling and the like, of the fundamental period of a timer counter.
However, since the variations in the level of generation of the reference voltage (Vref) in a thermometer are inherently independent of variations in the capability of refresh of the DRAM device, it is mandatory with the temperature system to match (trim) these two sorts of the variations at plural temperature points. This poses a serious problem in a wafer test step (the step of applying a probe on a pad of a wafer chip to carry out an electrical test of a die).
In the practical manufacturing process for DRAM devices, only temperature trimming for two points (high temperature point and low temperature point) is feasible from the perspective of test cost. As a result, fails tend to be produced at a mid temperature range so that a large operating margin needs to be provided as the variations are taken into account. With the result that it is not possible to achieve marked temperature traceability.
On the other hand, the techniques pertinent to (b) are disclosed in e.g. the Patent Publications 1 and 2 and in Non-Patent Publication 1.
The Patent Publication 1 discloses a standby current decreasing method (data retention current decreasing method) in a memory system employing the DRAM. As shown in FIG. 1 herein, a computer includes, in addition to a DRAM, an error correction encoding circuit and an error correction decoding circuit (error correction circuit), a refresh interval control circuit, a timer 2, a temperature sensor, a refresh circuit and a timer 1.
As the configuration of a DRAM device, provided with the ECC (error-checking and correction) encoding circuit and the decoding circuit as well as the refresh period control circuit, reference is made to the description of Patent Publications 2 and 4, indicated hereinbelow.
The operation of the system shown in FIG. 1 will now be described. First, in the usual write (WRITE) operation, the encoding operation is carried out at all times, so that parity data are written in a parity domain provided from the outset in the DRAM. Alternatively, on entry to the data retention operating mode (self refresh mode), data of all bits are read to an ECC encoding circuit to generate and write parity data of the entire data. Refresh period control is then exercised in accordance with the algorithm shown in FIG. 2.
During the operation for data retention, all bit refresh  pause (e.g. refresh interval) is repeated. Each time all bit refresh is carried out, all data are read to an error correction decoding circuit (error correction circuit) to carry out error detection and correction. If there is no error, the refresh period is extended (elongated) by a preset multiplication factor k1 and if there is any error, the row in error is copied. Or, the refresh period is shortened in dependence upon the number of errors. By repetition of the above sequence of operations, the refresh period is allowed to converge to an optimum value.
On the other hand, the number of errors detected (error rate) is controlled to be within the gamut of the error correction capability of the error correction decoding circuit (error correction circuit).
In the Non-Patent Publication 1, this technique was substantiated by evaluation on a real operating apparatus. This technique, if grasped as being equipped in a DRAM, may be summarized as follows:
In a data retention mode, carrying an on-chip ECC (realizing low power dissipation by power control), all data are read to an ECC decoding circuit to monitor the error rate.
The refresh cycle is shortened and elongated in case the error rate measured is higher and lower than a preset value, respectively. By so doing, refresh period temperature compensation may be enabled as the error rate is maintained at lower than the ability for correction.
As the configuration for variably controlling the refresh period based on the error rate of the memory cells, there is disclosed in e.g. Patent Publication 4 a semiconductor integrated circuit device including an error rate selection circuit booted for the data retention mode to read plural data held in a dynamic memory circuit to generate check bits for error detection and correction for storage in a supplementary memory circuit. Plural items of data and check bits associated therewith are read by an ECC circuit, at a constant refresh period, to effect error detection and correction. A first detection signal indicating the absence of error is integrated, a second detection signal, indicating the presence of error, is integrated with a weighting factor larger than that of the first detection signal, the detection signals are summed in the manner of subtracting the first stated integrated value, the refresh period is elongated a predetermined length of time when the integrated value exceeds a predetermined value and the refresh period is shortened a predetermined length of time when the integrated value has become smaller than a predetermined value.
There is also known a configuration in which, with the data retention mode, tail bits inferior in the capability (real power) of pause refresh are corrected for errors by the ECC circuit and masked, and the refresh period is elongated up to one second to realize the saving in power usage (Patent Publication 2). As for temperature dependency of pause refresh characteristics (temperature dependency of tail bits and normal bits), see the above Patent Publication 2 (e.g. FIGS. 10 and 11). As for details of the ECC circuit (ECC codec), as later described, reference is made to e.g. Patent Publication 3.
[Patent Publication 1]
JP Patent Kokai Publication JP-A-11-213659
[Patent Publication 2]
JP Patent Kokai Publication JP-P2002-056671A
[Patent Publication 3]
JP Patent Kokai Publication JP-2004-152378A
[Patent Publication 4]
JP Patent Kokai Publication JP-P2002-025229A
[Non-Patent Publication 1]
DFT'99 (1999 IEEE International Symposium on Defect and Fault Capability in VLSI systems), pp. 311-318